Xilinx releases ISE 13.4 design Kit

Xilinx announces the ISE 13.4 design Kit. The design suite provides public access to MicroBlaze microcontroller systems (MCS), new RX margin analysis and debugging capabilities for 28nm 7-series FPgas, And support for some reconfigurable features for Artix™-7 series and Virtex®-7 XT devices.

MicroBlaze MCS significantly simplifies microcontroller design

MicroBlaze MCS is a new addition to Xilinx's LogiCORE IP core solutions offering turnkey microcontroller solutions to Xilinx customers. It includes a MicroBlaze processor, local memory for program and data storage, and tightly coupled GPIOs, clocks, interrupt controllers, and other standard peripherals.

MCS is widely supported by many Xilinx FPGA family devices and is pre-configured to help hardware developers simplify deployment. Not only will software developers find familiar tools such as the Xilinx Software Development Kit (SDK), command line gcc, Xilinx microprocessor Debugger (XMD), and the MicroBlaze API that uses the same standard as larger processor configurations, but hardware developers will also be pleased to find that, In addition to being supported by Cadence, Mentor and Xilinx emulation solutions, MicroBlaze processors and all Xilinx embedded IP cores are now supported by Synopsys VCS emulators. MicroBlaze MCS is now included in all versions of the ISE Design Suite and ISE WebPACK and is compatible with the AutoESL™ Advanced Integrated Tool v2011.4.

New RX margin analysis tool

The ChipScope  Pro tool, available in ISE version 13.4, now offers an RX margin analysis tool that helps engineers optimize signal quality and reduce design bit error rate (BER). The RX margin analysis tool uses a two-dimensional eye scan statistical algorithm to characterize and optimize channel quality interactively in real time or during post-processing.

The fourth generation part can be reconfigured

The PlanAhead™ tool is now available to support some reconfigurable features for Artix-7 and Virtex-7 FPgas. The partially reconfigurable feature dynamically reconfigures logic modules without affecting the operation of other logic. This means that designers can use Artix-7 and Virtex-7 XT devices to build highly flexible systems that can change functions during operation or be updated remotely. In addition, partial reconfigurable capabilities also allow designers to reduce cost and design size by taking advantage of the benefits of time reuse by using smaller, fewer devices, reducing board space and minimizing storage requirements for bitstreams. Using smaller and fewer devices also reduces system power consumption, while replacing energy-intensive tasks minimizes the dynamic power consumption of the FPGA. This marks the first time that Xilinx will be able to offer partial reconfigurability for all 7 Series FPGA products, from low cost to high end.

Tom Feist, senior director of software and Tools marketing at Xilinx, said: "As hardware designs increasingly use point-to-point buses to send larger packets at faster transmission speeds, design engineers should pay more attention to the quality, bit error rate and margin required for such designs. Improving the productivity of our designers remains a top priority for Xilinx. The ISE 13.4 design suite further enricues and simplifies our development tools, ensuring their ease of use and supporting the deployment of our entire 7 series FPGA in these designs."