UltraSoC introduces the industry's first debug and analysis solution for the ARM AMBA 5 CHI Issue B conformance architecture

     UltraSoC, a leading developer of embedded analytics technology, has announced the full availability of a suite of debugging and monitoring intellectual property (IP) products for ARM's recently released AMBA 5 Coherent Hub Interface (CHI) Issue B specification. CHI Issue B is ARM's most advanced bus specification that supports complex system-on-chip (SoC) designs, and UltraSoC's monitoring and debugging offerings are unique in meeting the needs of designers working with the CHI Issue B specification.

     As a semiconductor IP product, UltraSoC's monitoring and debugging solutions provide reliable testing and help resolve issues for next-generation conformance cache SoC designs based on the CHI Issue B specification, enabling customers to benefit from the enhanced capabilities of the CHI Issue B specification. Enhance its security, data throughput, and latency. Dealing with conformance issues is becoming increasingly important for designers of complex systems, and UltraSoC has been chosen to speak on the topic at this year's ARM TechCon, which will take place October 24-26, 2017 at the Santa Clara Convention Center.

     By supporting CHI Issue B, UltraSoC continues its path of providing feature-rich system-level monitoring and debugging solutions that far exceed the performance of vendor-specific systems such as ARM's CoreSight. Designers can use UltraSoC's products as a "full coverage," which gives them access to features not provided by their traditional debug systems, or they can choose UltraSoC to completely replace these systems. This holistic approach to debugging is particularly beneficial in multi-core designs, as UltraSoC offers support for all common different CPU architectures and supports open source processor platforms such as RISC-V.

     "CHI is an increasingly important protocol that provides critical performance for on-chip networking of SOCs; But it's also a very challenging standard to design, especially with the new release of Issue B." Says GadgePanesar, CTO of UltraSoC. "Simple statistical performance is useful, but not nearly enough; This requires teams like UltraSoC, which are focused on monitoring and debugging, to come up with a solution to support this. This is the tremendous power that the ARM ecosystem can provide, that customers can leverage the expertise of a third-party solution provider like UltraSoC to help designers quickly and easily solve problems like consistent design immediately."

     Modern SOCs, especially those used in highly complex data centers, enterprise IT systems, or automotive applications, rely on flawless, efficient interconnectivity with on-chip networking hubs. The AMBA 5 CHI specification was developed in order to ensure that this internal interconnection does not become a bottleneck due to increased traffic and system complexity. Designers can choose how to implement CHI based on power consumption, performance, and chip area requirements. However, in these SoC designs and system choices, there are often various potential problems that can affect system performance, such as traffic issues related to cache consistency. By using the monitoring IP developed by UltraSoC for CHI Issue B, designers of these complex SOCs are able to quickly check performance while diagnosing and predicting such issues.

     The CHI Issue B specification incorporates a number of significant updates that can be used directly to improve latency and throughput, with the two most significant improvements being far-atomic operations and cache hiding. The far-atom operation supports internal interconnection to realize high-frequency update of shared data; Cache hiding is to enable low latency channels, and support accelerators or input/output devices to hide critical data in a CPU cache. To learn more about the new AMBA 5 CHI Issue B specification, atomic manipulation and cache hiding, as well as other performance improvements such as direct data transfer, visit the ARM blog.

     UltraSoC released the industry's first monitoring and debugging IP product for the earlier (Issue A)AMBA 5 CHI NoC specification last year, extending its protocol-aware monitor product line for on-chip interconnections while also supporting debugging and fine-tuning of NoC networking networks. Since then, UltraSoC has worked closely with a number of leading customers to develop a CHI Issue B solution that can be used to validate the way protocol customization is implemented to accelerate the overall integration of the chip design and to adjust the NoC to minimize the bus overhead.