Silicon Labs introduces the lowest jitter network synchronous clock chip

     Silicon Labs, a leading provider of high-performance clock solutions for Internet infrastructure applications, announced the industry's highest performing and cost-effective packet-switched network synchronous clock IC. The new Si5348 clock IC is a highly integrated, standards-compliant solution with the best jitter performance, the smallest size in the industry and the lowest power consumption. The Si5348 clock IC enables hardware designers to implement Synchronous Ethernet(SyncE), IEEE 1588v2, and wireless and telecommunications infrastructure, broadband networks such as G.fast DSL and PON), common frequency conversions in data center applications provide the ideal "clock tree on chip" solution.

     SyncE and IEEE 1588 have become increasingly popular methods for implementing network synchronization in packet switching. With the increasing popularity of these technologies, network device designers are demanding clock solutions that are more flexible, cost-effective, and easy to integrate into existing hardware architectures. Traditional network synchronous clocks usually use the more rigid synchronous clock chip architecture developed from the traditional Stratum 3 clock IC, which is not optimized for chip package size, power consumption, performance.

     Compared to traditional synchronous clock schemes, the Si5348 clock scheme has a 50% reduction in package size, 35% reduction in power consumption and 80% reduction in jitter. These advantages enable hardware designers to simplify the difficulty of synchronous design of packet networks and improve the performance of the system. The Si5348 architecture uses Silicon Labs' market-proven fourth-generation DSPLL® technology to provide a clock solution with the best jitter performance, fully meeting IEEE 1588, SyncE and Stratum3 clock requirements, enabling the chip to be used in a wide range of clock architecture applications for clock cards and line cards. In addition, the Si5348 clock is designed to interoperate easily with IEEE 1588 software running on an external host processor, further simplifying system integration.

     James Wilson, Director of Clock Product Marketing at Silicon Labs, said: "Currently, networks are transitioning from circuit switched systems to packet switched systems in order to improve efficiency, flexibility and cost effectiveness. With the widespread adoption of SyncE and IEEE 1588, device manufacturers are looking for solutions that minimize costs and reduce the complexity of adding packet-switched network synchronization to their designs. "Silicon Labs' new Si5348 packet-network synchronous clock offers optimal jitter performance, frequency flexibility, power efficiency and size, enabling hardware designers to optimize product designs with on-chip clock tree solutions."

     In packet clock applications, highly stable oscillators play a key role in defining overall network performance such as frequency, timing and phase accuracy. The network topology typically specifies the type of temperature-controlled crystal oscillator (TCXO) or thermostatic crystal oscillator (OCXO) required for each node in the network. The Si5348 clock supports a universal reference clock input port, which enables the chip to be used with any frequency TCXO/OCXO.

     As part of the Si5348 product development, Silicon Labs has partnered with Rakon to deliver comprehensive solutions for a wide range of SyncE and IEEE 1588 applications. Ullas Kumar, Application Marketing Manager at Rakon, said: "Rakon offers the industry's broadest portfolio of TCXO and OCXO products for SyncE and IEEE 1588 applications. "By partnering with Silicon Labs, we are providing our customers with a timing solution that can easily optimize their applications with superior frequency, stability, longevity and cost, while ensuring compatibility with the ITU-T specifications required by MTIE and TDEV."