Silicon Labs introduces PCI Express timing chips

Silicon Labs announced the expansion of its PCI Express (PCIe) clock generator and clock buffer portfolio to provide the industry's broadest range of clock solutions to meet the stringent requirements of the PCIe Gen 1/2/3 standard. Silicon Labs' expanded PCIe timing portfolio includes the existing Si5214x clock generator and Si5315x clock buffer for power - and cost-sensitive PCIe applications. It also includes a Si5335 network custom clock generator/buffer for FPGA and SoC design applications that require support for multiple differential clock formats while also complying with PCIe standards.

PCIe interconnect standards have been widely adopted in a wide range of applications, including: consumer electronics, blade servers, storage, embedded computing, IP gateways, and industrial systems. PCIe interfaces are also available for FPGA and SoC devices, providing designers with flexible and high-performance in-system data transfer solutions. Silicon Labs uses its patented mixed-signal technology to provide a flexible clock solution for PCIe designs to meet the needs of different markets and applications.

Mike Petrowski, general manager of timing products at Silicon Labs, said: "By bringing a 'one-stop shop' timing IC supply model to the PCIe market, we offer our customers the maximum flexibility to choose the best clock solution for their PCIe application needs, and our expanded portfolio of PCIe timing solutions is a complete complement to developers' current clock options. This includes minimizing power consumption, enhancing signal integration, and reducing costs, while also providing the industry's highly customized clock generators and buffers for FPGA-based designs."

Available PCIe clock solution

The Si5214x clock generator and Si5315x clock buffer product families offer the highest performance in the industry with 2-9 clock outputs. The new PCIe clock generator and buffer have twice the power efficiency of other clock solutions, and lower power consumption helps reduce heat dissipation and the need for additional cooling components and power regulators; At the same time, the chip meets PCIe's maximum jitter tolerance of 50%, which improves system stability and reduces bit error rate.

To further simplify design complexity, the Si5214x and Si5315x products utilize output buffering technology to integrate all external terminal resistors, reducing component count, BOM cost, board area, and power consumption. As the smallest PCIe clock device on the market, the new clock generator and buffer are ideal for space-constrained applications.

To overcome electromagnetic interference (EMI) and radio frequency interference (RFI), the Si5214x and Si5315x product families feature programmable edge rate and distortion control for each individual output. With the built-in I2C interface, developers need no more components to fine-tune signals and fix integrity problems in operation. This signal integrity adjustment capability enables products to better meet EMI requirements and reduces time to market for PCIe board designs.

Network custom 4-way clock generator/buffer

The Si5335 clock generator/Buffer IC is the industry's most customizable clock solution, specifically tailored to the timing challenges faced by PCIe and FPGA-based applications. Through the Silicon Labs website www.silabs.com/Clockbuilder is easy to use ClockBuilder ™ Web configuration utility, the customer can get the factory customized within 2 weeks, Si5335 pin control device (no minimum order limit), The Si5335 output can be configured with up to four output frequencies in any combination ranging from 1-350 MHz. A single part model can specify up to three unique device configurations, so the Si5335 can replace three independent clock generators or buffers, allowing developers to reuse custom Si5335 devices in multiple designs.

The Si5335 clock generator/buffer IC offers up to five user-assignable control pins to simplify PCIe and FPGAS based system design, and uses PCIe compatible spread spectrum clock options to simplify EMI compatibility. The Si5335 device uses Silicon Labs' patented MultiSynth fractional division technology, giving it subpicosecond jitter performance at any frequency synthesis on each output clock. The Si5335 exceeds the performance requirements of the PCIe, Ethernet, and Marine storage industry standards with a maximum jitter of 0.45ps (rms), more than twice the PCIe 3.0 jitter performance requirement of 1ps.

The Si5335 simplifies the challenge of multi-chip clocks and reduces the number of clock generators and buffers by supporting any combination of differential formats such as LVPECL, LVDS, CML, and single-ended formats such as LVCMOS, with the chip supporting any combination of 4 differential outputs or up to 8 LVCMOS outputs. The flexibility of the output format makes it easy for designers to adapt to the multiple output signal formats and power supply voltages that are common in PCIe, FPGA, and SoC embedded applications.