ON Semiconductor showcases energy-efficient 3D sensor stacking technology

     ON Semiconductor successfully evaluated performance and demonstrated the first fully featured stacked CMOS image sensor. Compared to traditional monolithic, non-stacked designs, the sensor's bare chip takes up less space, has higher pixel performance, and has better power consumption. This technology has been successfully implemented and performance has been verified in a test chip with 1.1 micron (µm) pixels, and will be launched in production form later this year.

     Traditional sensor designs using monolithic substrate processes require separate bare chip regions to support pixel arrays and auxiliary circuits. With 3D layering, the pixel arrays and auxiliary circuits can be fabricated separately on different substrates and then stacked together using silicon perforation technology (TSV). In this way, the pixel array can cover the basic circuit for a more efficient bare chip distribution. This approach allows design engineers to optimize various parts of the sensor, such as imaging performance, cost, power, and bare chip size.

     The optimization of pixel array can improve the pixel performance, reduce the noise level and enhance the pixel response. The underlying circuit can also use stricter design rules to reduce power consumption. The reduced total board space supports today's advanced camera modules that integrate optical image stabilization (OIS) and additional data storage capabilities in the same footprint.

     Sandor Bama, vice president of technology for ON Semiconductor's Image Sensors Division, said: "3D layering is an exciting breakthrough that improves our ability to optimize future sensors at ON Semiconductor. This technology provides manufacturing and design flexibility, ensuring that our entire sensor family remains a performance leader."