Infineon introduces a 25-150V OptiMOS™ source base power MOSFET in a PQFN package with double-sided cooling

     The design of future power electronics systems will continue to advance to achieve the highest levels of performance and power density. In response to this trend, Infineon Technologies offers a new source base power MOSFET in a 3.3 x 3.3 mm2 PQFN package that covers a voltage range of 25-150 V and is available in two different configurations: Bottom cooling (BSC) and double cooling (DSC). The new product family provides important performance improvements at the semiconductor device level, offers an attractive solution for DC-DC power conversion, and opens up new possibilities for system innovation in server, communications, OR-ing, battery protection, power tools, and charger applications.

     The new product family uses Infineon's latest MOSFET product technology and leading packaging technology to take system performance to the next level. Inside the source base (SD) package, the source contacts of the MOSFET wafer are flipped and oriented toward the sole side of the package, and then welded to the PCB. In addition, the package has an improved drain copper clip design inside the top of the chip, enabling a market-leading chip/package area ratio.

     As system sizes continue to shrink, two key factors - reducing power losses and improving heat dissipation - become critical. Infineon's new product family offers a 25 percent reduction in on-resistance (RDS(on) compared to the current market leader PQFN 3.3 x 3.3 mm² drain-bottom package. Infineon's double-sided heat dissipation, PQFN package, OptiMOS™ source base power MOSFETs provide an enhanced thermal interface that conducts power losses from the switching device to the heat sink. The double-sided cooling structure can connect the power switch to the heat sink in the most direct way, and its power consumption capacity is three times higher than that of the bottom-cooling, source bottom-power MOSFETs.

     The new product family offers two different pin arrangements that provide great flexibility for PCB routing. Using the pin arrangement of the traditional standard gate layout, the existing drain base design can be quickly and easily modified. The pin arrangement with the gate centered layout provides a new possibility for multiple devices to be connected in parallel, and can minimize the distance between the driver chip and the gate. The new generation 25-150 V OptiMOS™ source base power MOSFETs in PQFN 3.3 x 3.3 mm² package deliver superior continuous current capability up to 298A for the highest system performance.